月別アーカイブ: 2014年11月

ツッコミされないソースコード素材 

漫画とかでソースコードとか演出に使う時に、ツッコミを受けないための素材です。
全部自分で書いたものです。
商用／同人／改変フリーで引用元の記載もいりません。
VHDLなのでソフト系の技術者には分からないのがウリです。
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entity DVDP is
 Port ( ADRGB : out STD_LOGIC_VECTOR (15 downto 0);
 CLK : in STD_LOGIC;
 RESET : in STD_LOGIC;
 VSYNC : out STD_LOGIC;
 HSYNC : out STD_LOGIC;
 DE : out STD_LOGIC;
 DCLK : out STD_LOGIC;
 CLK574 : out STD_LOGIC;
 SRAMD : inout STD_LOGIC_VECTOR (7 downto 0);
 SRAM_WR : out STD_LOGIC;
 SRAM_OE : out STD_LOGIC;
 MAINRAM_A : out STD_LOGIC_VECTOR (13 downto 0);
 MAINRAM_D : in STD_LOGIC_VECTOR (7 downto 0);
 PALROM_A : out STD_LOGIC_VECTOR (10 downto 0);
 PALROM_D : in STD_LOGIC_VECTOR (15 downto 0);
 LINEBUF_WR : out STD_LOGIC;
 LINEBUF_AIN : out STD_LOGIC_VECTOR (9 downto 0);
 LINEBUF_DIN : in STD_LOGIC_VECTOR (15 downto 0);
 LINEBUF_DOUT : out STD_LOGIC_VECTOR (15 downto 0);
 LINEBUF_AOUT : out STD_LOGIC_VECTOR (9 downto 0);
 TEST_DIN : in STD_LOGIC_VECTOR (7 downto 0);
 TEST_A : out STD_LOGIC_VECTOR (11 downto 0));
end DVDP;
 
architecture Behavioral of DVDP is
signal HCOUNT : std_logic_vector(9 downto 0);
signal VCOUNT : std_logic_vector(8 downto 0);
signal RGB : std_logic_vector(15 downto 0);
signal HSYNC_IN : std_logic;
signal VSYNC_IN : std_logic;
signal DISP_H : std_logic;
signal DISP_V : std_logic;
signal VIDEO_A : std_logic_vector(12 downto 0);
signal temp_ADDR : std_logic_vector(15 downto 0);
signal crosshatch : std_logic;
 
begin
 crosshatch <= '1' when (HCOUNT(4 downto 0)="00000") or (VCOUNT(3 downto 0)="0000") else '0';
 
 ADRGB <= RGB;
 HSYNC <= HSYNC_IN;
 VSYNC <= VSYNC_IN;
  
 SRAM_WR <= '1';
 SRAM_OE <= '1';
 MAINRAM_A <= "00000000000000";
 PALROM_A <="00000000000";
 LINEBUF_WR <= '0';
 LINEBUF_DOUT <="0000000000000000";
 LINEBUF_AOUT <= "0000000000";
 TEST_A <="000000000000";
  
 DE <= DISP_H and DISP_V;
 DCLK <= HCOUNT(0);
 CLK574 <= not HCOUNT(0);
 
 process (HCOUNT,VCOUNT) begin
 if (crosshatch='1') then
 RGB <= "1111111111111111";
 else
 RGB <= "00000" & HCOUNT(9 downto 4) & VCOUNT(8 downto 4);
 end if;
 end process;
  
 process (VCOUNT) begin
 if (VCOUNT >= "011110111" and VCOUNT <= "011111101") then
 VSYNC_IN <= '0';
 else
 VSYNC_IN <= '1';
 end if;
 if (VCOUNT < "011100000") then --224
 DISP_V <= '1';
 else
 DISP_V <= '0';
 end if;
 end process;
  
 process (HCOUNT) begin
 if (HCOUNT >= "1010100101" and HCOUNT <= "1011101000") then
 HSYNC_IN <= '0';
 else
 HSYNC_IN <= '1';
 end if;
  
 if (HCOUNT <= "1000000000") then
 DISP_H <='1';
 else
 DISP_H <='0';
 end if;
 end process;
 
 process (CLK,RESET) begin
 if (RESET = '1') then
 HCOUNT <= "0000000000";
 VCOUNT <= "000000000";
 elsif (CLK'event and CLK='1') then
 if ( HCOUNT = "1110001101" ) then --909
 HCOUNT <= "0000000000";
 if (VCOUNT = "100000101") then --261
 VCOUNT <= "000000000";
 else
 VCOUNT <= VCOUNT + '1';
 end if;
 else
 HCOUNT <= HCOUNT + '1' ;
 end if;
  
 end if;
 end process;
 
 
end Behavioral;